1. Field of the Invention
The present invention relates to the design and operation of erasable and programmable non-volatile memory devices. More particularly, the present invention relates to circuits and algorithms for erasing memory cells in FLASH EPROM devices with wordline level retry.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. One popular class of non-volatile memory cell is known as the erasable-programmable read only memory (EPROM). Two popular EPROM designs are distinguished in the manner in which isolation of the memory cells is carried out. The first member of this class is referred to as the EEPROM. The second member of this class is known as the FLASH EPROM which uses a higher density format.
Both the FLASH EPROM and EEPROM technologies are based on a memory cell which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons which causes the turn-on threshold of the memory cell to increase. Thus, when programmed the cell, will not turn on (i.e., it will remain non-conductive, when addressed with a read potential applied to its control gate). The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
Both the FLASH EPROM and EEPROM memory cells suffer from the problem of over-erasure. Over-erasure occurs if, during the erasing step, too many electrons are removed from the floating gate leaving a slight positive charge. This biases the memory cell slightly on, so that a small current may leak through the memory cell even when it is not addressed. A number of over-erased cells along a given bitline can cause an accumulation of leakage current sufficient to cause a false reading. The regular EEPROM design uses either a two transistor cell structure which includes a pass gate that isolates the memory cell from the bitline or a split-gate structure which behaves like two transistors in series to isolate unselected cells, so that unselected memory cells do not contribute leakage current to the bitline. The higher density FLASH EPROM cell does not use the isolation transistor or split-gate, so over-erasure causes a significant problem in the FLASH EPROM design.
When floating gate cells are over-erased, it makes it difficult to reprogram the cells successfully using hot electron programming, particularly with embedded algorithms in the integrated circuits that cannot handle special cases.
In the past, commercial FLASH EPROM designs have included circuitry for verifying the success of programming and erasing steps. See, for instance, U.S. Pat. No. 4,875,188, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth.
Traditionally, erase verification begins at address 0000 (hex) and continues through the array to the last address, or until data other than FF (hex) is encountered. If a byte fails to verify, the entire device is re-erased. This re-erase operation may result in over-erasure of memory cells that had passed the erase verify voltage margin during the initial erase operation. Also, the re-erase operation is time consuming, requiring re-verification of the entire array after each re-erase operation.
To address these problems, FLASH EPROM designs have been developed to include circuitry for programming, erasing, verifying, re-erasing, and re-verifying at a memory level smaller than the entire array. In these designs the memory array is divided into a plurality of sectors (blocks), each of which composes an erase retry unit. See U.S. Pat. No. 5,414,664 entitled FLASH EPROM WITH BLOCK ERASE FLAGS FOR OVER-ERASE PROTECTION, invented by Lin et al., the entire contents of which are hereby incorporated by reference.
Meanwhile, low power design parameters and high speed read requirements continue to exert a strong motivation to lower the erase voltage (ERS-VT) that is used to erase the memory cells. However, the lower most boundary of the ERS-VT is limited by the over-erase and the soft program current issues. As a result, the VT distribution control is becoming more and more crucial. What is needed, therefore, is a better way to control the ERS-VT.
The ERS-VT could be better controlled by design if only a small unit of to-be-erased FLASH EPROM memory cells exposed to the next erase high voltage pulses. Even in sector divided memory arrays, the erase retry unit is traditionally large (e.g., 512 Kb).
Accordingly, an erase verify and re-erase system for FLASH EPROM devices is needed which provides enhanced protection against over-erase due to repeated erasures, and which further speeds up the verify sequence.